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Espressif Systems /ESP32-P4 /RMT /INT_CLR

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Interpret as INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0_TX_END_INT_CLR)CH0_TX_END_INT_CLR 0 (CH1_TX_END_INT_CLR)CH1_TX_END_INT_CLR 0 (CH2_TX_END_INT_CLR)CH2_TX_END_INT_CLR 0 (CH3_TX_END_INT_CLR)CH3_TX_END_INT_CLR 0 (TX_CH0_ERR_INT_CLR)TX_CH0_ERR_INT_CLR 0 (TX_CH1_ERR_INT_CLR)TX_CH1_ERR_INT_CLR 0 (TX_CH2_ERR_INT_CLR)TX_CH2_ERR_INT_CLR 0 (TX_CH3_ERR_INT_CLR)TX_CH3_ERR_INT_CLR 0 (CH0_TX_THR_EVENT_INT_CLR)CH0_TX_THR_EVENT_INT_CLR 0 (CH1_TX_THR_EVENT_INT_CLR)CH1_TX_THR_EVENT_INT_CLR 0 (CH2_TX_THR_EVENT_INT_CLR)CH2_TX_THR_EVENT_INT_CLR 0 (CH3_TX_THR_EVENT_INT_CLR)CH3_TX_THR_EVENT_INT_CLR 0 (CH0_TX_LOOP_INT_CLR)CH0_TX_LOOP_INT_CLR 0 (CH1_TX_LOOP_INT_CLR)CH1_TX_LOOP_INT_CLR 0 (CH2_TX_LOOP_INT_CLR)CH2_TX_LOOP_INT_CLR 0 (CH3_TX_LOOP_INT_CLR)CH3_TX_LOOP_INT_CLR 0 (CH4_RX_END_INT_CLR)CH4_RX_END_INT_CLR 0 (CH5_RX_END_INT_CLR)CH5_RX_END_INT_CLR 0 (CH6_RX_END_INT_CLR)CH6_RX_END_INT_CLR 0 (CH7_RX_END_INT_CLR)CH7_RX_END_INT_CLR 0 (RX_CH4_ERR_INT_CLR)RX_CH4_ERR_INT_CLR 0 (RX_CH5_ERR_INT_CLR)RX_CH5_ERR_INT_CLR 0 (RX_CH6_ERR_INT_CLR)RX_CH6_ERR_INT_CLR 0 (RX_CH7_ERR_INT_CLR)RX_CH7_ERR_INT_CLR 0 (CH4_RX_THR_EVENT_INT_CLR)CH4_RX_THR_EVENT_INT_CLR 0 (CH5_RX_THR_EVENT_INT_CLR)CH5_RX_THR_EVENT_INT_CLR 0 (CH6_RX_THR_EVENT_INT_CLR)CH6_RX_THR_EVENT_INT_CLR 0 (CH7_RX_THR_EVENT_INT_CLR)CH7_RX_THR_EVENT_INT_CLR 0 (TX_CH3_DMA_ACCESS_FAIL_INT_CLR)TX_CH3_DMA_ACCESS_FAIL_INT_CLR 0 (RX_CH7_DMA_ACCESS_FAIL_INT_CLR)RX_CH7_DMA_ACCESS_FAIL_INT_CLR

Description

Interrupt clear bits

Fields

CH0_TX_END_INT_CLR

Set this bit to clear theCH0_TX_END_INT interrupt.
CH1_TX_END_INT_CLR

Set this bit to clear theCH1_TX_END_INT interrupt.
CH2_TX_END_INT_CLR

Set this bit to clear theCH2_TX_END_INT interrupt.
CH3_TX_END_INT_CLR

Set this bit to clear theCH3_TX_END_INT interrupt.
TX_CH0_ERR_INT_CLR

Set this bit to clear theCH0_ERR_INT interrupt.
TX_CH1_ERR_INT_CLR

Set this bit to clear theCH1_ERR_INT interrupt.
TX_CH2_ERR_INT_CLR

Set this bit to clear theCH2_ERR_INT interrupt.
TX_CH3_ERR_INT_CLR

Set this bit to clear theCH3_ERR_INT interrupt.
CH0_TX_THR_EVENT_INT_CLR

Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
CH1_TX_THR_EVENT_INT_CLR

Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
CH2_TX_THR_EVENT_INT_CLR

Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt.
CH3_TX_THR_EVENT_INT_CLR

Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt.
CH0_TX_LOOP_INT_CLR

Set this bit to clear theCH0_TX_LOOP_INT interrupt.
CH1_TX_LOOP_INT_CLR

Set this bit to clear theCH1_TX_LOOP_INT interrupt.
CH2_TX_LOOP_INT_CLR

Set this bit to clear theCH2_TX_LOOP_INT interrupt.
CH3_TX_LOOP_INT_CLR

Set this bit to clear theCH3_TX_LOOP_INT interrupt.
CH4_RX_END_INT_CLR

Set this bit to clear theCH4_RX_END_INT interrupt.
CH5_RX_END_INT_CLR

Set this bit to clear theCH5_RX_END_INT interrupt.
CH6_RX_END_INT_CLR

Set this bit to clear theCH6_RX_END_INT interrupt.
CH7_RX_END_INT_CLR

Set this bit to clear theCH7_RX_END_INT interrupt.
RX_CH4_ERR_INT_CLR

Set this bit to clear theCH4_ERR_INT interrupt.
RX_CH5_ERR_INT_CLR

Set this bit to clear theCH5_ERR_INT interrupt.
RX_CH6_ERR_INT_CLR

Set this bit to clear theCH6_ERR_INT interrupt.
RX_CH7_ERR_INT_CLR

Set this bit to clear theCH7_ERR_INT interrupt.
CH4_RX_THR_EVENT_INT_CLR

Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt.
CH5_RX_THR_EVENT_INT_CLR

Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt.
CH6_RX_THR_EVENT_INT_CLR

Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt.
CH7_RX_THR_EVENT_INT_CLR

Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt.
TX_CH3_DMA_ACCESS_FAIL_INT_CLR

Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt.
RX_CH7_DMA_ACCESS_FAIL_INT_CLR

Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd